New Dates and Locations Coming this Summer and Fall.

To be notified of all future Masterclass dates and locations , or to schedule a class, please email

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"It’s time to simplify things. IC integration has not only radically changed life on planet Earth, it has also changed Signal Integrity (SI)." 

This class exists to inform Hardware and SI engineers about what you need to do to achieve Signal Integrity, in Practice. "Doubling data rate isn't something to be afraid of, it's simply what we do," says your instructor, Donald Telian, who has doubled data rate more than a dozen times throughout his 40-year career. After solving SI for every kind of electronic product and often pioneering how its SI will be achieved, Telian is now stepping out of his design cave to teach this 2-day class detailing the essentials of SI. Covering topics from the primary causes of SI failures, Telian quickly guides the class from what should I worry about to how to fix it. This class removes SI mystery using a blend of instruction, hands-on exercises, and follow-up office hours to ensure attendees succeed when they return to their desks and projects. Register now to attend a live class near you, space is limited in each location to offer you the best learning experience. We'll see you there!

Course Outline

Day 1    Telian's 7-Steps Methodology for  Successful SI

SI is focused on high-speed serial links, and Telian's 7 Steps encapsulates how to balance hardware and software for a successful implementation. Day one juxtaposes the 7 steps against the most common causes of SI failure, so engineers know how to prioritize design tasks and where to focus effort. Attendees finish day one with a sense of "I can do this," regardless of how mysterious and complex SI seemed at the start of the day.

Agenda

          8:00      Breakfast, Intros, & The SI Hangout (formal start at 9 am sharp)

          9:00      New School SI & Serial Link Dominance

         10:00    The Dominant SI Failures are NOT What You Think - how to avoid/fix them

         11:00    Hardware SI: Understanding and Fixing Discontinuities

         12:00    Catered Lunch

         1:00      Hardware SI: Budgeting and Managing Loss

          1:30      Lab 1:  Eyes, Loss, Gbps & BERs

          2:00      Yikes I've Got Stubs, and Route/Stackup/Fabrication Secret Sauce

          3:30      Intro to Software SI: Equalization Registers and Firmware

          4:00      Day 1 Wrapped.  Who’s gonna RUN?!

          4:45      5k Run (optional)

          6:00      Hosted Masterclass Dinner

Day 2     A Deeper Dive  into SI with Hands-On Labs

On day two Telian takes a deeper look at topics such as equalization (EQ) and crosstalk, with a practical focus on what automation (e.g., design tools, auto-negotiation) will handle and what it will not. Serial links have revolutionized the practice because much of SI has gone inside the ICs in the form of EQ. “While we address what must be done in hardware, because higher data rate SI hinges on EQ, it's essential hardware engineers acquire a working knowledge of its use, " says Telian. "My focus on EQ is part of what makes this class unique, and the hands-on labs quickly boot up attendees on how to use it effectively, "Improper software EQ is the number one reason links fail, with number two being hardware discontinuities. Telian concludes. "Using hands-on labs on day two ensures attendees experience both the power and limitations of EQ, further underscoring how to blend hardware and software to achieve robust SI.

Agenda  

          8:00      Breakfast, The SI Hangout, Day 1 Aha's

          9:00      EQ Types, Characteristics, Pros/Cons, Impact on Eyes and Pulse Response

          10:30    Lab 2:  Deploying EQ Elements in a System

          11:00    Pulse Response Interplay with Eyes and EQ - how to optimize/fix links

          12:00    Catered Lunch

          1:00      Lab 3:  Open Your Eyes by Combining/Tuning EQ - pulse response secrets

          2:00      Class Competition (friendly style)

          2:30      Let's Brave:  Jitter, Standards, Measurements, DDRx, SI & Layout Synergies

          3:30      Signal Integrity Futures - Where do we go from here?

          4:00      Day 2 Wrapped, Experiment/Complete Labs, The SI Hangout

          5:00      Masterclass is Done - time to go rock your designs!

What's Included

• 2-Day Workshop with all course materials
• A free 30-day MATLAB^® license for all students
• A hard-back copy of Donald Telian's book Signal Integrity, in Practice
• 3 months of Office hours with Donald Telian Course Discord Server
• All Meals are included, including a group dinner out after day one
• Free Parking
• Optional participation in Telian's "Beat the Old Guy" 5K run and associated prizes
• Most importantly a memorable, fun, and engaging learning experience!

Not Included 

• Travel and accommodations costs (For Hotel recommendations click top right gray menu bar)
• Ground Transportation during the event
• A dull and boring learning experience that puts you to sleep!